62 if ((
fd = fopen (file,
"r")) == NULL) {
64 file, strerror (errno));
73 if (
fd != stdin) fclose (
fd);
117 for (; values != NULL; values = values->
next) v->
add (values->
value);
144 for (pairs = def->
pairs; pairs != NULL; pairs = pairs->
next)
146 if (pairs->
value->
var && strcmp (pairs->
key,
"Param")) {
193 for (pairs = def->
pairs; pairs != NULL; pairs = pairs->
next)
249 for (i = 0, nodes = def->
nodes; nodes; nodes = nodes->
next, i++)
250 if (i < c->getSize ())
254 for (pairs = def->
pairs; pairs != NULL; pairs = pairs->
next) {
255 if (pairs->
value == NULL) {
316 p->setDefault (
true);
322 p->setDefault (
true);
350 if (!strcmp (type,
"SUBST"))
void setSubcircuit(char *)
void insertAnalysis(analysis *)
int netlist_checker_variables(environment *env)
void setEnv(environment *e)
bool hasProperty(const char *)
int netlist_checker(environment *env)
circuit_creator_t circreate
void setName(const char *)
base class for qucs circuit elements.
struct property_t::@6 defaultval
void netlist_destroy(void)
void addProperty(property *)
void setSize(int)
Set the number of ports the circuit element has.
void setSubstrate(substrate *s)
void setValue(nr_double_t val)
static qucs::hash< module > modules
substrate * getSubstrate(void)
void insertCircuit(circuit *)
#define PROP_IS_PROP(prop)
#define PROP_IS_VAL(prop)
void setEnv(environment *e)
void netlist_status(void)
struct definition_t * definition_root
void setConstant(eqn::constant *c)
bool isVariableSized(void)
class for performing circuit analyses.
void setNonLinear(bool l)
void setNode(int, const char *, int intern=0)
struct property_t * optional
The environment class definition.
void addNodeset(nodeset *)
analysis_creator_t anacreate
variable * getVariable(char *)
struct definition_t * netlist_unchain_definition(struct definition_t *root, struct definition_t *cand)
void logprint(int level, const char *format,...)
struct definition_t * next
void addVariable(variable *, bool pass=true)
void setSubstrate(substrate *)