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pad4bit.cpp
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1 /*
2  * pad4bit.cpp - device implementations for pad4bit module
3  *
4  * This is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2, or (at your option)
7  * any later version.
8  *
9  */
10 #include <stdlib.h>
11 #include <QtGui>
12 #include "pad4bit.h"
13 #include "node.h"
14 #include "main.h"
15 
16 pad4bit::pad4bit()
17 {
18  Type = isComponent; // Analogue and digital component.
19  Description = QObject::tr ("4bit pattern generator verilog device");
20 
21  Props.append (new Property ("Number", "0", false,
22  QObject::tr ("pad output value")));
23 
24  createSymbol ();
25  tx = x1 + 4;
26  ty = y2 + 4;
27  Model = "pad4bit";
28  Name = "Y";
29 }
30 
31 Component * pad4bit::newOne()
32 {
33  pad4bit * p = new pad4bit();
34  p->Props.getFirst()->Value = Props.getFirst()->Value;
35  p->recreate(0);
36  return p;
37 }
38 
39 Element * pad4bit::info(QString& Name, char * &BitmapFile, bool getNewOne)
40 {
41  Name = QObject::tr("4Bit Pattern");
42  BitmapFile = (char *) "pad4bit";
43 
44  if(getNewOne) return new pad4bit();
45  return 0;
46 }
47 
48 void pad4bit::createSymbol()
49 {
50  Lines.append(new Line(-60, -50, 30,-50,QPen(Qt::darkGreen,2)));
51  Lines.append(new Line( 30, -50, 30, 50,QPen(Qt::darkGreen,2)));
52  Lines.append(new Line( 30, 50,-60, 50,QPen(Qt::darkGreen,2)));
53  Lines.append(new Line(-60, 50,-60,-50,QPen(Qt::darkGreen,2)));
54 
55  Lines.append(new Line( 40,-30, 30,-30,QPen(Qt::darkGreen,2))); // A
56  Lines.append(new Line( 40,-10, 30,-10,QPen(Qt::darkGreen,2))); // B
57  Lines.append(new Line( 40, 10, 30, 10,QPen(Qt::darkGreen,2))); // C
58  Lines.append(new Line( 40, 30, 30, 30,QPen(Qt::darkGreen,2))); // D
59 
60  Texts.append(new Text(-58,-46, " 0 1 2 3", Qt::darkGreen, 12.0));
61  Texts.append(new Text(-58,-23, " 4 5 6 7", Qt::darkGreen, 12.0));
62  Texts.append(new Text(-58, 0, " 8 9 10 11", Qt::darkGreen, 12.0));
63  Texts.append(new Text(-58, 23, "12 13 14 15", Qt::darkGreen, 12.0));
64 
65  Ports.append(new Port(40, 30)); // D
66  Ports.append(new Port(40, 10)); // C
67  Ports.append(new Port(40,-10)); // B
68  Ports.append(new Port(40,-30)); // A
69 
70  x1 = -64; y1 = -54;
71  x2 = 40; y2 = 54;
72 }
73 
74 QString pad4bit::vhdlCode( int )
75 {
76  QString v = Props.at(0)->Value;
77  QString s1, s2, s3, s ="";
78 
79  QString A = Ports.at(0)->Connection->Name;
80  QString B = Ports.at(1)->Connection->Name;
81  QString C = Ports.at(2)->Connection->Name;
82  QString D = Ports.at(3)->Connection->Name;
83 
84  s1 = "\n "+Name+":process\n"+
85  " variable n_" + Name + " : integer := " + v + ";\n" +
86  " begin\n";
87  s2 = " case n_" + Name + " is\n" +
88  " when 0 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '0';\n"+
89  " when 1 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '1';\n"+
90  " when 2 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '0';\n"+
91  " when 3 => "+A+" <= '0'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '1';\n"+
92  " when 4 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '0';\n"+
93  " when 5 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '1';\n"+
94  " when 6 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '0';\n"+
95  " when 7 => "+A+" <= '0'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '1';\n"+
96  " when 8 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '0';\n"+
97  " when 9 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '0'; "+D+" <= '1';\n"+
98  " when 10 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '0';\n"+
99  " when 11 => "+A+" <= '1'; "+B+" <= '0'; "+C+" <= '1'; "+D+" <= '1';\n"+
100  " when 12 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '0';\n"+
101  " when 13 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '0'; "+D+" <= '1';\n"+
102  " when 14 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '0';\n"+
103  " when 15 => "+A+" <= '1'; "+B+" <= '1'; "+C+" <= '1'; "+D+" <= '1';\n"+
104  " when others => null;\n"
105  " end case;\n";
106  s3 = " end process;\n";
107  s = s1+s2+s3;
108  return s;
109 }
110 
111 QString pad4bit::verilogCode( int )
112 {
113  QString v = Props.at(0)->Value;
114 
115  QString l = "";
116  QString l1, l2, l3;
117 
118  QString A = Ports.at(0)->Connection->Name;
119  QString B = Ports.at(1)->Connection->Name;
120  QString C = Ports.at(2)->Connection->Name;
121  QString D = Ports.at(3)->Connection->Name;
122 
123  QString AR = "A_reg" + Name + A;
124  QString BR = "B_reg" + Name + B;
125  QString CR = "C_reg" + Name + C;
126  QString DR = "C_reg" + Name + D;
127 
128  l1 = "\n // "+Name+" 4bit pattern generator\n"+
129  " assign "+A+" = "+AR+";\n"+
130  " reg "+AR+" = 0;\n"+
131  " assign "+B+" = "+BR+";\n"+
132  " reg "+BR+" = 0;\n"+
133  " assign "+C+" = "+CR+";\n"+
134  " reg "+CR+" = 0;\n"+
135  " assign "+D+" = "+DR+";\n"+
136  " reg "+DR+" = 0;\n"+
137  " initial\n";
138  l2 = " begin\n"
139  " case ("+v+")\n"+
140  " 0 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 0; "+DR+" = 0; end\n"+
141  " 1 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 0; "+DR+" = 1; end\n"+
142  " 2 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 1; "+DR+" = 0; end\n"+
143  " 3 : begin "+AR+" = 0; "+BR+" = 0; "+CR+" = 1; "+DR+" = 1; end\n"+
144  " 4 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 0; "+DR+" = 0; end\n"+
145  " 5 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 0; "+DR+" = 1; end\n"+
146  " 6 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 1; "+DR+" = 0; end\n"+
147  " 7 : begin "+AR+" = 0; "+BR+" = 1; "+CR+" = 1; "+DR+" = 1; end\n"+
148  " 8 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 0; "+DR+" = 0; end\n"+
149  " 9 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 0; "+DR+" = 1; end\n"+
150  " 10 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 1; "+DR+" = 0; end\n"+
151  " 11 : begin "+AR+" = 1; "+BR+" = 0; "+CR+" = 1; "+DR+" = 1; end\n"+
152  " 12 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 0; "+DR+" = 0; end\n"+
153  " 13 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 0; "+DR+" = 1; end\n"+
154  " 14 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 1; "+DR+" = 0; end\n"+
155  " 15 : begin "+AR+" = 1; "+BR+" = 1; "+CR+" = 1; "+DR+" = 1; end\n"+
156  " endcase\n";
157  l3 = " end\n";
158  l = l1+l2+l3;
159  return l;
160 }
Component::Lines
Q3PtrList< Line > Lines
Definition: component.h:67
pad4bit::verilogCode
QString verilogCode(int)
Definition: pad4bit.cpp:111
Element::Type
int Type
Definition: element.h:152
Element::y1
int y1
Definition: element.h:153
Component::tx
int tx
Definition: component.h:78
Element::y2
int y2
Definition: element.h:153
Port
Definition: element.h:72
Element::x1
int x1
Definition: element.h:153
main.h
Definitions and declarations for the main application.
Component::ty
int ty
Definition: component.h:78
Component::Props
Q3PtrList< Property > Props
Definition: component.h:72
pad4bit::createSymbol
void createSymbol()
Definition: pad4bit.cpp:48
Text
Definition: element.h:82
Line
Definition: element.h:48
Element
Superclass of all schematic drawing elements.
Definition: element.h:142
Component::Ports
Q3PtrList< Port > Ports
Definition: component.h:70
pad4bit::pad4bit
pad4bit()
Definition: pad4bit.cpp:16
Component::Name
QString Name
Definition: component.h:80
Component::Texts
Q3PtrList< Text > Texts
Definition: component.h:71
Component::Model
QString Model
Definition: component.h:80
Component::Description
QString Description
Definition: component.h:81
isComponent
#define isComponent
Definition: element.h:110
pad4bit::newOne
Component * newOne()
Definition: pad4bit.cpp:31
Element::x2
int x2
Definition: element.h:153
Component::recreate
virtual void recreate(Schematic *)
Definition: component.h:39
pad4bit::vhdlCode
QString vhdlCode(int)
Definition: pad4bit.cpp:74
pad4bit::info
static Element * info(QString &, char *&, bool getNewOne=false)
Definition: pad4bit.cpp:39
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