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comp_4bit.cpp
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1 /***************************************************************************
2  comp_4bit
3  -----------
4  begin : December 2008
5  copyright : (C) 2008 by Mike Brinson
6  email : mbrin72043@yahoo.co.uk
7  ***************************************************************************/
8 
9 /*
10  * comp_4bit.cpp - device implementations for comp_4bit module
11  *
12  * This is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2, or (at your option)
15  * any later version.
16  *
17  */
18 #include <QtGui>
19 #include "comp_4bit.h"
20 #include "node.h"
21 #include "main.h"
22 
23 comp_4bit::comp_4bit()
24 {
25  Type = isComponent; // Analogue and digital component.
26  Description = QObject::tr ("4bit comparator verilog device");
27 
28  Props.append (new Property ("TR", "6", false,
29  QObject::tr ("transfer function high scaling factor")));
30  Props.append (new Property ("Delay", "1 ns", false,
31  QObject::tr ("output delay")
32  +" ("+QObject::tr ("s")+")"));
33 
34  createSymbol ();
35  tx = x1 + 19;
36  ty = y2 + 4;
37  Model = "comp_4bit";
38  Name = "Y";
39 }
40 
41 Component * comp_4bit::newOne()
42 {
43  comp_4bit * p = new comp_4bit();
44  p->Props.getFirst()->Value = Props.getFirst()->Value;
45  p->recreate(0);
46  return p;
47 }
48 
49 Element * comp_4bit::info(QString& Name, char * &BitmapFile, bool getNewOne)
50 {
51  Name = QObject::tr("4Bit Comparator");
52  BitmapFile = (char *) "comp_4bit";
53 
54  if(getNewOne) return new comp_4bit();
55  return 0;
56 }
57 
58 void comp_4bit::createSymbol()
59 {
60  Lines.append(new Line(-40, -90, 40,-90,QPen(Qt::darkBlue,2)));
61  Lines.append(new Line( 40, -90, 40,100,QPen(Qt::darkBlue,2)));
62  Lines.append(new Line( 40, 100,-40,100,QPen(Qt::darkBlue,2)));
63  Lines.append(new Line(-40, 100,-40,-90,QPen(Qt::darkBlue,2)));
64 
65  Lines.append(new Line(-60,-50,-40,-50,QPen(Qt::darkBlue,2))); // X0
66  Lines.append(new Line(-60,-30,-40,-30,QPen(Qt::darkBlue,2))); // X1
67  Lines.append(new Line(-60,-10,-40,-10,QPen(Qt::darkBlue,2))); // X2
68  Lines.append(new Line(-60, 10,-40, 10,QPen(Qt::darkBlue,2))); // X3
69  Lines.append(new Line(-60, 30,-40, 30,QPen(Qt::darkBlue,2))); // Y0
70  Lines.append(new Line(-60, 50,-40, 50,QPen(Qt::darkBlue,2))); // Y1
71  Lines.append(new Line(-60, 70,-40, 70,QPen(Qt::darkBlue,2))); // Y2
72  Lines.append(new Line(-60, 90,-40, 90,QPen(Qt::darkBlue,2))); // Y3
73  Lines.append(new Line( 40, 30, 60, 30,QPen(Qt::darkBlue,2))); // L
74  Lines.append(new Line( 40, 10, 60, 10,QPen(Qt::darkBlue,2))); // G
75  Lines.append(new Line( 40,-10, 60,-10,QPen(Qt::darkBlue,2))); // E
76 
77  Texts.append(new Text(-25,-85, "COMP", Qt::darkBlue, 12.0));
78 
79  Texts.append(new Text(-25,-40, "{", Qt::darkBlue, 16.0));
80  Texts.append(new Text(-15,-35, "X", Qt::darkBlue, 12.0));
81  Texts.append(new Text(-35,-63, "0", Qt::darkBlue, 12.0));
82  Texts.append(new Text(-35,-43, "1", Qt::darkBlue, 12.0));
83  Texts.append(new Text(-35,-23, "2", Qt::darkBlue, 12.0));
84  Texts.append(new Text(-35, -3, "3", Qt::darkBlue, 12.0));
85  Texts.append(new Text(-25, 42, "{", Qt::darkBlue, 16.0));
86  Texts.append(new Text(-15, 47, "Y", Qt::darkBlue, 12.0));
87  Texts.append(new Text(-35, 17, "0", Qt::darkBlue, 12.0));
88  Texts.append(new Text(-35, 37, "1", Qt::darkBlue, 12.0));
89  Texts.append(new Text(-35, 57, "2", Qt::darkBlue, 12.0));
90  Texts.append(new Text(-35, 77, "3", Qt::darkBlue, 12.0));
91  Texts.append(new Text( 5, 17, "X<Y", Qt::darkBlue, 12.0));
92  Texts.append(new Text( 5, -3, "X>Y", Qt::darkBlue, 12.0));
93  Texts.append(new Text( 5,-23, "X=Y", Qt::darkBlue, 12.0));
94 
95  Ports.append(new Port(-60,-50)); // X0
96  Ports.append(new Port(-60,-30)); // X1
97  Ports.append(new Port(-60,-10)); // X2
98  Ports.append(new Port(-60, 10)); // X3
99  Ports.append(new Port(-60, 30)); // Y0
100  Ports.append(new Port(-60, 50)); // Y1
101  Ports.append(new Port(-60, 70)); // Y2
102  Ports.append(new Port(-60, 90)); // Y3
103  Ports.append(new Port( 60, 30)); // L
104  Ports.append(new Port( 60, 10)); // G
105  Ports.append(new Port( 60,-10)); // E
106 
107  x1 = -60; y1 = -94;
108  x2 = 60; y2 = 104;
109 }
110 
111 QString comp_4bit::vhdlCode( int )
112 {
113  QString s="";
114 
115  QString td = Props.at(1)->Value; // delay time
116  if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
117  td += ";\n";
118 
119  QString X0 = Ports.at(0)->Connection->Name;
120  QString X1 = Ports.at(1)->Connection->Name;
121  QString X2 = Ports.at(2)->Connection->Name;
122  QString X3 = Ports.at(3)->Connection->Name;
123  QString Y0 = Ports.at(4)->Connection->Name;
124  QString Y1 = Ports.at(5)->Connection->Name;
125  QString Y2 = Ports.at(6)->Connection->Name;
126  QString Y3 = Ports.at(7)->Connection->Name;
127  QString L = Ports.at(8)->Connection->Name;
128  QString G = Ports.at(9)->Connection->Name;
129  QString E = Ports.at(10)->Connection->Name;
130 
131  s = "\n "+Name+":process ("+X0+", "+X1+", "+X2+", "+X3+", "+Y0+", "+Y1+", "+Y2+", "+Y3+")\n"+
132  " variable P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11 : std_logic;\n"+
133  " begin\n"+
134  " P0 := not ("+X0+" xor "+Y0+");\n"+
135  " P1 := not ("+X1+" xor "+Y1+");\n"+
136  " P2 := not ("+X2+" xor "+Y2+");\n"+
137  " P3 := not ("+X3+" xor "+Y3+");\n"+
138  " P4 := (not "+X0+") and "+Y0+";\n"+
139  " P5 := (not "+X1+") and "+Y1+";\n"+
140  " P6 := (not "+X2+") and "+Y2+";\n"+
141  " P7 := (not "+X3+") and "+Y3+";\n"+
142  " P8 := "+X0+" and (not "+Y0+");\n"+
143  " P9 := "+X1+" and (not "+Y1+");\n"+
144  " P10 := "+X2+" and (not "+Y2+");\n"+
145  " P11 := "+X3+" and (not "+Y3+");\n"+
146  " "+L+" <= P7 or (P3 and P6) or (P3 and P2 and P5) or (P3 and P2 and P1 and P4)"+td+
147  " "+G+" <= P11 or (P3 and P10) or (P3 and P2 and P9) or (P3 and P2 and P1 and P8)"+td+
148  " "+E+" <= P3 and P2 and P1 and P0"+td+
149  " end process;\n";
150  return s;
151 }
152 
153 QString comp_4bit::verilogCode( int )
154 {
155  QString l="";
156 
157  QString td = Props.at(1)->Value; // delay time
158  if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
159 
160  QString X0 = Ports.at(0)->Connection->Name;
161  QString X1 = Ports.at(1)->Connection->Name;
162  QString X2 = Ports.at(2)->Connection->Name;
163  QString X3 = Ports.at(3)->Connection->Name;
164  QString Y0 = Ports.at(4)->Connection->Name;
165  QString Y1 = Ports.at(5)->Connection->Name;
166  QString Y2 = Ports.at(6)->Connection->Name;
167  QString Y3 = Ports.at(7)->Connection->Name;
168  QString L = Ports.at(8)->Connection->Name;
169  QString G = Ports.at(9)->Connection->Name;
170  QString E = Ports.at(10)->Connection->Name;
171 
172  QString LR = "L_reg" + Name + L;
173  QString GR = "G_reg" + Name + G;
174  QString ER = "E_reg" + Name + E;
175 
176  l = "\n // "+Name+" 4bit comparator\n"+
177  " assign "+L+" = "+LR+";\n"+
178  " reg "+LR+" = 0;\n"+
179  " assign "+G+" = "+GR+";\n"+
180  " reg "+GR+" = 0;\n"+
181  " assign "+E+" = "+ER+";\n"+
182  " reg "+ER+" = 0;\n"+
183  " reg P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11;\n"+
184  " always @ ("+X0+" or "+X1+" or "+X2+" or "+X3+" or "+Y0+" or "+Y1+" or "+Y2+" or "+Y3+")\n"+
185  " begin\n"+
186  " P0 = ~("+X0+" ^ "+Y0+");\n"+
187  " P1 = ~("+X1+" ^ "+Y1+");\n"+
188  " P2 = ~("+X2+" ^ "+Y2+");\n"+
189  " P3 = ~("+X3+" ^ "+Y3+");\n"+
190  " P4 = (~"+X0+") && "+Y0+";\n"+
191  " P5 = (~"+X1+") && "+Y1+";\n"+
192  " P6 = (~"+X2+") && "+Y2+";\n"+
193  " P7 = (~"+X3+") && "+Y3+";\n"+
194  " P8 = "+X0+" && (~"+Y0+");\n"+
195  " P9 = "+X1+" && (~"+Y1+");\n"+
196  " P10 = "+X2+" && (~"+Y2+");\n"+
197  " P11 = "+X3+" && (~"+Y3+");\n"+
198  " "+LR+" <="+td+" P7 || (P3 && P6) || (P3 && P2 && P5) || (P3 && P2 && P1 && P4)"+";\n"+
199  " "+GR+" <="+td+" P11 || (P3 && P10) || (P3 && P2 && P9) || (P3 && P2 && P1 && P8)"+";\n"+
200  " "+ER+" <="+td+" P3 && P2 && P1 && P0"+";\n"+
201  " end\n";
202 
203  return l;
204 }
Component::Lines
Q3PtrList< Line > Lines
Definition: component.h:67
Element::Type
int Type
Definition: element.h:152
Element::y1
int y1
Definition: element.h:153
VHDL_Delay
bool VHDL_Delay(QString &td, const QString &Name)
Definition: main.cpp:493
Component::tx
int tx
Definition: component.h:78
comp_4bit::createSymbol
void createSymbol()
Definition: comp_4bit.cpp:58
Element::y2
int y2
Definition: element.h:153
Port
Definition: element.h:72
Element::x1
int x1
Definition: element.h:153
comp_4bit::comp_4bit
comp_4bit()
Definition: comp_4bit.cpp:23
comp_4bit.h
comp_4bit::newOne
Component * newOne()
Definition: comp_4bit.cpp:41
Verilog_Delay
bool Verilog_Delay(QString &td, const QString &Name)
Definition: main.cpp:555
main.h
Definitions and declarations for the main application.
Component::ty
int ty
Definition: component.h:78
Component::Props
Q3PtrList< Property > Props
Definition: component.h:72
Text
Definition: element.h:82
Line
Definition: element.h:48
Element
Superclass of all schematic drawing elements.
Definition: element.h:142
comp_4bit::info
static Element * info(QString &, char *&, bool getNewOne=false)
Definition: comp_4bit.cpp:49
comp_4bit::verilogCode
QString verilogCode(int)
Definition: comp_4bit.cpp:153
comp_4bit::vhdlCode
QString vhdlCode(int)
Definition: comp_4bit.cpp:111
Component::Ports
Q3PtrList< Port > Ports
Definition: component.h:70
Component::Name
QString Name
Definition: component.h:80
Component::Texts
Q3PtrList< Text > Texts
Definition: component.h:71
Component::Model
QString Model
Definition: component.h:80
Component::Description
QString Description
Definition: component.h:81
isComponent
#define isComponent
Definition: element.h:110
Element::x2
int x2
Definition: element.h:153
Component::recreate
virtual void recreate(Schematic *)
Definition: component.h:39
comp_4bit
Definition: comp_4bit.h:16
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