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logical_buf.cpp
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1 /***************************************************************************
2  logical_buf.cpp
3  -----------------
4  begin : Sat Nov 8 2008
5  copyright : (C) 2008 by Stefan Jahn
6  email : stefan@lkcc.org
7  ***************************************************************************/
8 
9 /***************************************************************************
10  * *
11  * This program is free software; you can redistribute it and/or modify *
12  * it under the terms of the GNU General Public License as published by *
13  * the Free Software Foundation; either version 2 of the License, or *
14  * (at your option) any later version. *
15  * *
16  ***************************************************************************/
17 #include <QtGui>
18 #include "main.h"
19 #include "logical_buf.h"
20 #include "schematic.h"
21 #include "node.h"
22 
23 
25 {
26  Type = isComponent; // both analog and digital
27  Description = QObject::tr("logical buffer");
28 
29  // the list order must be preserved !!!
30  Props.append(new Property("V", "1 V", false,
31  QObject::tr("voltage of high level")));
32  Props.append(new Property("t", "0", false,
33  QObject::tr("delay time")));
34  Props.append(new Property("TR", "10", false,
35  QObject::tr("transfer function scaling factor")));
36 
37  // this must be the last property in the list !!!
38  Props.append(new Property("Symbol", "old", false,
39  QObject::tr("schematic symbol")+" [old, DIN40900]"));
40 
41  createSymbol();
42  tx = x1+4;
43  ty = y2+4;
44  Model = "Buf";
45  Name = "Y";
46 }
47 
48 // -------------------------------------------------------
49 QString Logical_Buf::vhdlCode(int NumPorts)
50 {
51  QString s = " " + Ports.getFirst()->Connection->Name + " <= " +
52  Ports.getLast()->Connection->Name;
53 
54  if(NumPorts <= 0) { // no truth table simulation ?
55  QString td = Props.at(1)->Value;
56  if(!VHDL_Delay(td, Name)) return td;
57  s += td;
58  }
59 
60  s += ";\n";
61  return s;
62 }
63 
64 // -------------------------------------------------------
65 QString Logical_Buf::verilogCode(int NumPorts)
66 {
67  bool synthesize = true;
68  Port *pp = Ports.first();
69  QString s ("");
70 
71  if (synthesize) {
72  s = " assign";
73 
74  if(NumPorts <= 0) { // no truth table simulation ?
75  QString td = Props.at(1)->Value;
76  if(!Verilog_Delay(td, Name)) return td;
77  s += td;
78  }
79  s += " ";
80  s += pp->Connection->Name + " = "; // output port
81  pp = Ports.next();
82  s += pp->Connection->Name; // input port
83  s += ";\n";
84  }
85  return s;
86 }
87 
88 // -------------------------------------------------------
90 {
91  int xr;
92 
93  if(Props.getLast()->Value.at(0) == 'D') { // DIN symbol
94  Lines.append(new Line( 15,-20, 15, 20,QPen(Qt::darkBlue,2)));
95  Lines.append(new Line(-15,-20, 15,-20,QPen(Qt::darkBlue,2)));
96  Lines.append(new Line(-15, 20, 15, 20,QPen(Qt::darkBlue,2)));
97  Lines.append(new Line(-15,-20,-15, 20,QPen(Qt::darkBlue,2)));
98 
99  Texts.append(new Text(-11,-17, "1", Qt::darkBlue, 15.0));
100  xr = 15;
101  }
102  else { // old symbol
103  Lines.append(new Line(-10,-20,-10,20, QPen(Qt::darkBlue,2)));
104  Arcs.append(new Arc(-30,-20, 40, 30, 0, 16*90,QPen(Qt::darkBlue,2)));
105  Arcs.append(new Arc(-30,-10, 40, 30, 0,-16*90,QPen(Qt::darkBlue,2)));
106  Lines.append(new Line( 10,-5, 10, 5,QPen(Qt::darkBlue,2)));
107  xr = 10;
108  }
109 
110  Lines.append(new Line( xr, 0, 30, 0, QPen(Qt::darkBlue,2)));
111  Lines.append(new Line(-30, 0,-xr, 0, QPen(Qt::darkBlue,2)));
112  Ports.append(new Port( 30, 0));
113  Ports.append(new Port(-30, 0));
114 
115  x1 = -30; y1 = -23;
116  x2 = 30; y2 = 23;
117 }
118 
119 // -------------------------------------------------------
121 {
122  Logical_Buf* p = new Logical_Buf();
123  p->Props.getLast()->Value = Props.getLast()->Value;
124  p->recreate(0);
125  return p;
126 }
127 
128 // -------------------------------------------------------
129 Element* Logical_Buf::info(QString& Name, char* &BitmapFile, bool getNewOne)
130 {
131  Name = QObject::tr("Buffer");
132  BitmapFile = (char *) "buffer";
133 
134  if(getNewOne) return new Logical_Buf();
135  return 0;
136 }
Q3PtrList< Line > Lines
Definition: component.h:67
int Type
Definition: element.h:152
Definition: element.h:55
Node * Connection
Definition: element.h:79
int y1
Definition: element.h:153
bool VHDL_Delay(QString &td, const QString &Name)
Definition: main.cpp:493
Q3PtrList< struct Arc > Arcs
Definition: component.h:68
QString vhdlCode(int)
Definition: logical_buf.cpp:49
int tx
Definition: component.h:78
int y2
Definition: element.h:153
Definition: element.h:72
int x1
Definition: element.h:153
bool Verilog_Delay(QString &td, const QString &Name)
Definition: main.cpp:555
Definitions and declarations for the main application.
int ty
Definition: component.h:78
Q3PtrList< Property > Props
Definition: component.h:72
void createSymbol()
Definition: logical_buf.cpp:89
Definition: element.h:82
Definition: element.h:48
Superclass of all schematic drawing elements.
Definition: element.h:142
void recreate(Schematic *)
Definition: component.cpp:1250
Q3PtrList< Port > Ports
Definition: component.h:70
QString Name
Definition: component.h:80
Q3PtrList< Text > Texts
Definition: component.h:71
QString Model
Definition: component.h:80
QString Name
Definition: node.h:40
QString Description
Definition: component.h:81
#define isComponent
Definition: element.h:110
Component * newOne()
static Element * info(QString &, char *&, bool getNewOne=false)
int x2
Definition: element.h:153
QString verilogCode(int)
Definition: logical_buf.cpp:65