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gatedDlatch.cpp
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1 /***************************************************************************
2  gatedDlatch
3  -------------
4  begin : January 2009
5  copyright : (C) 2008 by Mike Brinson
6  email : mbrin72043@yahoo.co.uk
7  ***************************************************************************/
8 
9 /*
10  * gatedDlatch.cpp - device implementations for gatedDlatch module
11  *
12  * This is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2, or (at your option)
15  * any later version.
16  *
17  */
18 #include <QtGui>
19 #include "gatedDlatch.h"
20 #include "node.h"
21 #include "main.h"
22 
24 {
25  Type = isComponent; // Analogue and digital component.
26  Description = QObject::tr ("gated D latch verilog device");
27 
28  Props.append (new Property ("TR_H", "6", false,
29  QObject::tr ("cross coupled gate transfer function high scaling factor")));
30  Props.append (new Property ("TR_L", "5", false,
31  QObject::tr ("cross coupled gate transfer function low scaling factor")));
32  Props.append (new Property ("Delay", "1 ns", false,
33  QObject::tr ("cross coupled gate delay")
34  +" ("+QObject::tr ("s")+")"));
35 
36  createSymbol ();
37  tx = x1 + 19;
38  ty = y2 + 4;
39  Model = "gatedDlatch";
40  Name = "Y";
41 }
42 
44 {
45  gatedDlatch * p = new gatedDlatch();
46  p->Props.getFirst()->Value = Props.getFirst()->Value;
47  p->recreate(0);
48  return p;
49 }
50 
51 Element * gatedDlatch::info(QString& Name, char * &BitmapFile, bool getNewOne)
52 {
53  Name = QObject::tr("Gated D-Latch");
54  BitmapFile = (char *) "gatedDlatch";
55 
56  if(getNewOne) return new gatedDlatch();
57  return 0;
58 }
59 
61 {
62  Lines.append(new Line(-30, -40, 30,-40,QPen(Qt::darkBlue,2)));
63  Lines.append(new Line( 30, -40, 30, 40,QPen(Qt::darkBlue,2)));
64  Lines.append(new Line( 30, 40,-30, 40,QPen(Qt::darkBlue,2)));
65  Lines.append(new Line(-30, 40,-30, -40,QPen(Qt::darkBlue,2)));
66 
67  Lines.append(new Line(-50,-20,-30,-20,QPen(Qt::darkBlue,2))); // D
68  Lines.append(new Line(-50, 20,-30, 20,QPen(Qt::darkBlue,2))); // C
69  Lines.append(new Line( 40, 20, 50, 20,QPen(Qt::darkBlue,2))); // QB
70  Lines.append(new Line( 30,-20, 50,-20,QPen(Qt::darkBlue,2))); // Q
71 
72  Arcs.append(new Arc( 30, 15, 10, 10, 0, 16*360, QPen(Qt::darkBlue,2)));
73 
74  Texts.append(new Text(-25,-32, "D", Qt::darkBlue, 12.0));
75  Texts.append(new Text(-25, 7, "C", Qt::darkBlue, 12.0));
76  Texts.append(new Text( 11,-32, "Q", Qt::darkBlue, 12.0));
77  Texts.append(new Text( 11, 7, "Q", Qt::darkBlue, 12.0));
78  Texts.current()->over=true;
79 
80  Ports.append(new Port(-50,-20)); // D
81  Ports.append(new Port(-50, 20)); // C
82  Ports.append(new Port( 50, 20)); // QB
83  Ports.append(new Port( 50,-20)); // Q
84 
85  x1 = -50; y1 = -44;
86  x2 = 50; y2 = 44;
87 }
88 
89 QString gatedDlatch::vhdlCode( int )
90 {
91  QString s="";
92 
93  QString td = Props.at(2)->Value; // delay time
94  if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
95  td += ";\n";
96 
97  QString D = Ports.at(0)->Connection->Name;
98  QString C = Ports.at(1)->Connection->Name;
99  QString QB = Ports.at(2)->Connection->Name;
100  QString Q = Ports.at(3)->Connection->Name;
101 
102  s = "\n "+Name+":process ("+D+", "+C+")\n"+
103  " begin\n" +
104  " if ("+C+" = '1') then\n"+
105  " "+Q+" <= "+D+td+
106  " "+QB+" <= not "+D+td+
107  " end if;\n"+
108  " end process;\n";
109  return s;
110 }
111 
113 {
114  QString td = Props.at(2)->Value; // delay time
115  if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
116 
117  QString l = "";
118 
119  QString D = Ports.at(0)->Connection->Name;
120  QString C = Ports.at(1)->Connection->Name;
121  QString QB = Ports.at(2)->Connection->Name;
122  QString Q = Ports.at(3)->Connection->Name;
123 
124  QString QR = "Q_reg" + Name + Q;
125  QString QBR = "QB_reg" + Name + QB;
126 
127  l = "\n // "+Name+" gated d latch\n"+
128  " assign "+Q+" = "+QR+";\n"+
129  " reg "+QR+" = 0;\n"+
130  " assign "+QB+" = "+QBR+";\n"+
131  " reg "+QBR+" = 0;\n"+
132  " always @ ("+D+" or "+C+")\n"+
133  " begin\n"+
134  " if ("+C+" == 1)\n"+
135  " begin\n"+
136  " " +QR+" <="+td+" "+D+";\n"+
137  " " +QBR+" <="+td+" ~"+D+";\n" +
138  " end\n"+
139  " end\n";
140 
141  return l;
142 }
Q3PtrList< Line > Lines
Definition: component.h:67
int Type
Definition: element.h:152
Component * newOne()
Definition: gatedDlatch.cpp:43
Definition: element.h:55
int y1
Definition: element.h:153
bool VHDL_Delay(QString &td, const QString &Name)
Definition: main.cpp:493
static Element * info(QString &, char *&, bool getNewOne=false)
Definition: gatedDlatch.cpp:51
Q3PtrList< struct Arc > Arcs
Definition: component.h:68
int tx
Definition: component.h:78
int y2
Definition: element.h:153
Definition: element.h:72
int x1
Definition: element.h:153
QString verilogCode(int)
bool Verilog_Delay(QString &td, const QString &Name)
Definition: main.cpp:555
Definitions and declarations for the main application.
int ty
Definition: component.h:78
Q3PtrList< Property > Props
Definition: component.h:72
Definition: element.h:82
Definition: element.h:48
Superclass of all schematic drawing elements.
Definition: element.h:142
Q3PtrList< Port > Ports
Definition: component.h:70
void createSymbol()
Definition: gatedDlatch.cpp:60
QString Name
Definition: component.h:80
Q3PtrList< Text > Texts
Definition: component.h:71
QString Model
Definition: component.h:80
QString Description
Definition: component.h:81
QString vhdlCode(int)
Definition: gatedDlatch.cpp:89
#define isComponent
Definition: element.h:110
int x2
Definition: element.h:153
virtual void recreate(Schematic *)
Definition: component.h:39