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binarytogrey4bit.cpp
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1 /***************************************************************************
2  binarytogrey4bit
3  -------------------
4  begin : December 2008
5  copyright : (C) 2008 by Mike Brinson
6  email : mbrin72043@yahoo.co.uk
7  ***************************************************************************/
8 
9 /*
10  * binarytogrey4bit.cpp - device implementations for binarytogrey4bit module
11  *
12  * This is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2, or (at your option)
15  * any later version.
16  *
17  */
18 #include <QtGui>
19 #include "binarytogrey4bit.h"
20 #include "node.h"
21 #include "main.h"
22 
24 {
25  Type = isComponent; // Analogue and digital component.
26  Description = QObject::tr ("4bit binary to grey converter verilog device");
27 
28  Props.append (new Property ("TR", "6", false,
29  QObject::tr ("transfer function scaling factor")));
30  Props.append (new Property ("Delay", "1 ns", false,
31  QObject::tr ("output delay")
32  +" ("+QObject::tr ("s")+")"));
33 
34  createSymbol ();
35  tx = x1 + 19;
36  ty = y2 + 4;
37  Model = "binarytogrey4bit";
38  Name = "Y";
39 }
40 
42 {
44  p->Props.getFirst()->Value = Props.getFirst()->Value;
45  p->recreate(0);
46  return p;
47 }
48 
49 Element * binarytogrey4bit::info(QString& Name, char * &BitmapFile, bool getNewOne)
50 {
51  Name = QObject::tr("4Bit Bin2Grey");
52  BitmapFile = (char *) "binarytogrey4bit";
53 
54  if(getNewOne) return new binarytogrey4bit();
55  return 0;
56 }
57 
59 {
60  Lines.append(new Line(-30, -60, 30,-60,QPen(Qt::darkBlue,2)));
61  Lines.append(new Line( 30, -60, 30, 40,QPen(Qt::darkBlue,2)));
62  Lines.append(new Line( 30, 40,-30, 40,QPen(Qt::darkBlue,2)));
63  Lines.append(new Line(-30, 40,-30, -60,QPen(Qt::darkBlue,2)));
64 
65  Lines.append(new Line(-50,-30,-30,-30,QPen(Qt::darkBlue,2))); // B0
66  Lines.append(new Line(-50,-10,-30,-10,QPen(Qt::darkBlue,2))); // B1
67  Lines.append(new Line(-50, 10,-30, 10,QPen(Qt::darkBlue,2))); // B2
68  Lines.append(new Line(-50, 30,-30, 30,QPen(Qt::darkBlue,2))); // B3
69 
70  Lines.append(new Line( 30, 30, 50, 30,QPen(Qt::darkBlue,2))); // G3
71  Lines.append(new Line( 30, 10, 50, 10,QPen(Qt::darkBlue,2))); // G2
72  Lines.append(new Line( 30,-10, 50,-10,QPen(Qt::darkBlue,2))); // G1
73  Lines.append(new Line( 30,-30, 50,-30,QPen(Qt::darkBlue,2))); // G0
74 
75  Texts.append(new Text(-16,-59, "B", Qt::darkBlue, 12.0));
76  Texts.append(new Text( -2,-59, "/", Qt::darkBlue, 12.0));
77  Texts.append(new Text( 5,-59, "G", Qt::darkBlue, 12.0));
78 
79  Texts.append(new Text(-25,-43, "0", Qt::darkBlue, 12.0));
80  Texts.append(new Text(-25,-23, "1", Qt::darkBlue, 12.0));
81  Texts.append(new Text(-25, -3, "2", Qt::darkBlue, 12.0));
82  Texts.append(new Text(-25, 17, "3", Qt::darkBlue, 12.0));
83 
84  Texts.append(new Text( 15,-43, "0", Qt::darkBlue, 12.0));
85  Texts.append(new Text( 15,-23, "1", Qt::darkBlue, 12.0));
86  Texts.append(new Text( 15, -3, "2", Qt::darkBlue, 12.0));
87  Texts.append(new Text( 15, 17, "3", Qt::darkBlue, 12.0));
88 
89  Ports.append(new Port(-50,-30)); // B0
90  Ports.append(new Port(-50,-10)); // B1
91  Ports.append(new Port(-50, 10)); // B2
92  Ports.append(new Port(-50, 30)); // B3
93 
94  Ports.append(new Port( 50, 30)); // G3
95  Ports.append(new Port( 50, 10)); // G2
96  Ports.append(new Port( 50,-10)); // G1
97  Ports.append(new Port( 50,-30)); // G0
98 
99  x1 = -50; y1 = -64;
100  x2 = 50; y2 = 44;
101 }
102 
104 {
105  QString s="";
106 
107  QString td = Props.at(1)->Value; // delay time
108  if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
109  td += ";\n";
110 
111  QString B0 = Ports.at(0)->Connection->Name;
112  QString B1 = Ports.at(1)->Connection->Name;
113  QString B2 = Ports.at(2)->Connection->Name;
114  QString B3 = Ports.at(3)->Connection->Name;
115  QString G3 = Ports.at(4)->Connection->Name;
116  QString G2 = Ports.at(5)->Connection->Name;
117  QString G1 = Ports.at(6)->Connection->Name;
118  QString G0 = Ports.at(7)->Connection->Name;
119 
120 
121  s = "\n "+Name + ":process ("+B0+", "+B1+", "+B2+", "+B3+")\n" +
122  " begin\n"+
123  " "+G0+" <= "+B0+" xor "+B1+td+
124  " "+G1+" <= "+B1+" xor "+B2+td+
125  " "+G2+" <= "+B2+" xor "+B3+td+
126  " "+G3+" <= "+B3+td+
127  " end process;\n";
128  return s;
129 }
130 
132 {
133  QString td = Props.at(1)->Value; // delay time
134  if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
135 
136  QString B0 = Ports.at(0)->Connection->Name;
137  QString B1 = Ports.at(1)->Connection->Name;
138  QString B2 = Ports.at(2)->Connection->Name;
139  QString B3 = Ports.at(3)->Connection->Name;
140  QString G3 = Ports.at(4)->Connection->Name;
141  QString G2 = Ports.at(5)->Connection->Name;
142  QString G1 = Ports.at(6)->Connection->Name;
143  QString G0 = Ports.at(7)->Connection->Name;
144 
145  QString l = "";
146 
147  QString G0R = "net_reg" + Name + G0;
148  QString G1R = "net_reg" + Name + G1;
149  QString G2R = "net_reg" + Name + G2;
150  QString G3R = "net_reg" + Name + G3;
151 
152  l = "\n // " + Name + " 4bit binary to grey\n" +
153  " assign " + G0 + " = " + G0R + ";\n" +
154  " reg " + G0R + " = 0;\n" +
155  " assign " + G1 + " = " + G1R + ";\n" +
156  " reg " + G1R + " = 0;\n" +
157  " assign " + G2 + " = " + G2R + ";\n" +
158  " reg " + G2R + " = 0;\n" +
159  " assign " + G3 + " = " + G3R + ";\n" +
160  " reg " + G3R + " = 0;\n" +
161  " always @ ("+B0+" or "+B1+" or "+B2+" or "+B3+")\n" +
162  " begin\n"+
163  " "+G0R+" <="+td+" "+B0+" ^ "+B1+";\n"+
164  " "+G1R+" <="+td+" "+B1+" ^ "+B2+";\n"+
165  " "+G2R+" <="+td+" "+B2+" ^ "+B3+";\n"+
166  " "+G3R+" <="+td+" "+B3+";\n"+
167  " end\n";
168  return l;
169 }
Q3PtrList< Line > Lines
Definition: component.h:67
int Type
Definition: element.h:152
int y1
Definition: element.h:153
bool VHDL_Delay(QString &td, const QString &Name)
Definition: main.cpp:493
int tx
Definition: component.h:78
int y2
Definition: element.h:153
Definition: element.h:72
int x1
Definition: element.h:153
bool Verilog_Delay(QString &td, const QString &Name)
Definition: main.cpp:555
Definitions and declarations for the main application.
int ty
Definition: component.h:78
Component * newOne()
Q3PtrList< Property > Props
Definition: component.h:72
static Element * info(QString &, char *&, bool getNewOne=false)
QString verilogCode(int)
Definition: element.h:82
Definition: element.h:48
Superclass of all schematic drawing elements.
Definition: element.h:142
Q3PtrList< Port > Ports
Definition: component.h:70
QString Name
Definition: component.h:80
Q3PtrList< Text > Texts
Definition: component.h:71
QString Model
Definition: component.h:80
QString Description
Definition: component.h:81
#define isComponent
Definition: element.h:110
int x2
Definition: element.h:153
virtual void recreate(Schematic *)
Definition: component.h:39